Embodiments of the present inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device that can reduce power consumption in a low power mode while using a plurality of lanes, and a system including the same.
The peripheral component interconnect express (PCIe) is a high-speed serial computer expansion bus standard designed for replacing a PCI bus standard or a Peripheral Component Interconnect Extended (PCI-X) bus standard. The PCIe uses a lane. The lane includes two differential signaling pairs. One pair is used to receive data, and the other pair is used to transfer data. The PCIe uses a link which includes one, two, four, eight, twelve, sixteen, or thirty-two lanes.
Although a semiconductor device which supports the PCIe enters an L1 state or an L1 mode which is a low power mode, the semiconductor device needs to supply power to each of a plurality of physical medium attachment sub-layers (PMAs) connected to each of a plurality of lanes. Accordingly, although a semiconductor device which includes the plurality of PMAs and supports the PCIe operates in a low power mode, a substantially large amount of power is consumed by the plurality of PMAs which maintains a standby state.